Friday, February 20, 2026
4:00 PM -
5:00 PM
Moore B280
EE Devices Seminar
Series: EE Devices Seminar Series
Ultra-low noise Phase-locked Loop Technique
Taekwang Jang,
Associate Professor,
Dept. of Information Technology and Electrical Engineering,
ETH Zürich,
Speaker's Bio:
Taekwang Jang (S’06-M’13-SM’19) received his B.S. and M.S. in electrical engineering from KAIST, Korea, in 2006 and 2008, respectively. From 2008 to 2013, he worked at Samsung Electronics Company Ltd., Yongin, Korea, focusing on mixed-signal circuit design, including analog and all-digital phase-locked loops for communication systems and mobile processors. In 2017, he received his Ph.D. from the University of Michigan and worked as a post-doctoral research fellow at the same institution. In 2018, he joined ETH Zürich and currently works as an associate professor, leading the Energy-Efficient Circuits and Intelligent Systems group. He is also a member of the Competence Center for Rehabilitation Engineering and Science, and the chair of the IEEE Solid-State Circuits Society, Switzerland chapter. His research focuses on circuits and systems for highly energy-constrained applications such as wireless sensor nodes and biomedical interfaces. Essential building blocks such as a sensor interface, energy harvester, power converter, communication transceiver, frequency synthesizer, and data converters are his primary interests. He holds 15 patents and has (co)authored more than 100 peer-reviewed conferences and journal articles. He is the recipient of the 2024 IEEE Solid-State Circuits Society New Frontier Award, the SNSF Starting Grant, the IEEE ISSCC 2021 and 2022 Jan Van Vessem Award for Outstanding European Paper, the IEEE ISSCC 2022 Outstanding Forum Speaker Award, and the 2009 IEEE CAS Guillemin-Cauer Best Paper Award. Since 2022, he has been a TPC member of the IEEE International Solid-State Circuits Conference (ISSCC), IMD Subcommittee, and IEEE Asian Solid-State Circuits Conference (ASSCC), Analog Subcommittee. He also chaired the 2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Frequency Generation Subcommittee. Since 2023, he has been serving as an Associate Editor for the Journal of Solid-State Circuits (JSSC) and was appointed as a Distinguished Lecturer for the Solid-State Circuits Society in 2024.
Taekwang Jang (S’06-M’13-SM’19) received his B.S. and M.S. in electrical engineering from KAIST, Korea, in 2006 and 2008, respectively. From 2008 to 2013, he worked at Samsung Electronics Company Ltd., Yongin, Korea, focusing on mixed-signal circuit design, including analog and all-digital phase-locked loops for communication systems and mobile processors. In 2017, he received his Ph.D. from the University of Michigan and worked as a post-doctoral research fellow at the same institution. In 2018, he joined ETH Zürich and currently works as an associate professor, leading the Energy-Efficient Circuits and Intelligent Systems group. He is also a member of the Competence Center for Rehabilitation Engineering and Science, and the chair of the IEEE Solid-State Circuits Society, Switzerland chapter. His research focuses on circuits and systems for highly energy-constrained applications such as wireless sensor nodes and biomedical interfaces. Essential building blocks such as a sensor interface, energy harvester, power converter, communication transceiver, frequency synthesizer, and data converters are his primary interests. He holds 15 patents and has (co)authored more than 100 peer-reviewed conferences and journal articles. He is the recipient of the 2024 IEEE Solid-State Circuits Society New Frontier Award, the SNSF Starting Grant, the IEEE ISSCC 2021 and 2022 Jan Van Vessem Award for Outstanding European Paper, the IEEE ISSCC 2022 Outstanding Forum Speaker Award, and the 2009 IEEE CAS Guillemin-Cauer Best Paper Award. Since 2022, he has been a TPC member of the IEEE International Solid-State Circuits Conference (ISSCC), IMD Subcommittee, and IEEE Asian Solid-State Circuits Conference (ASSCC), Analog Subcommittee. He also chaired the 2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Frequency Generation Subcommittee. Since 2023, he has been serving as an Associate Editor for the Journal of Solid-State Circuits (JSSC) and was appointed as a Distinguished Lecturer for the Solid-State Circuits Society in 2024.
The generation of high-purity clock sources is becoming more crucial in today's communication systems. With the advent of advanced communication systems such as 5G wireless radios and ultra high-speed wireline transceivers, the required clock jitter is now below 50 fs. While recent PLLs have achieved such a jitter specification with a power consumption of just a few mW, they are typically tested with ultra-low noise XOs consuming 100s to 1000s mW, overlooking holistic optimization. This talk discusses two PLL topologies that actively optimize the noise and power of the entire frequency generation and synthesis chain.
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